Memory device and method of reducing ground bounce in a memory device
US6088288A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1999 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reducing power supply current transients in a memory array caused by a simultaneous change in logic state of numerous CMOS digital circuits during a memory write cycle. Write driver enable signals (ENT, ENC) and bitcell enable signals (WBC1-WBC24) are sequentially delayed in time during the write cycle through use of the propagation delay of inverters (INV1-INV24-7). The sequential time delay reduces the number of circuits that are simultaneously changing logic state at any given time during the write cycle. The power supply current transient is transformed from a single, large change in current to a series of smaller changes displaced in time from each other during the write cycle. The ground bounce of the power supply network attributed to the current transient is significantly reduced, such change in ground potential being directly related to the magnitude of the current transient and its rate of change with respect to time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.