Apparatus for reducing jitter in a desynchronizer
US6088413A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Apr 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/076
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus, to be used in a desynchronizer, for minimizing the output jitter of the desynchronizer. The desynchronizer is assumed to include a bit buffer for staging data that is to be output. The desynchronizer is also assumed to include a means for decoding the input signal to determine how justification opportunities in the input signal are used and therefore what justification bits must be leaked by the desynchronizer. The apparatus and method of the present invention uses the information about the incoming justification bits or incoming justification bytes and the state of the buffer to determine the longest possible time to wait before issuing a command to momentarily speed up or delay outputting the next data unit from the bit buffer. This speeding up or delay is caused by sending a clock signal to the bit buffer that is shifted in phase by a small amount, thereby spreading out the effect of an incoming positive or negative justification bit or byte over many periods of the output clock of the desynchronizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.