Processor with multiple execution units and local and global register bypasses
US6088784A · kind A · utility
10Cited by
48References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1999 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for data processing between multiple execution units using local and global register bypasses is disclosed. In one embodiment, the device contains a register file, at least two bypass circuits, a plurality of execution units, and a control circuit. Each bypass circuit connects to at least one execution unit. The control circuit, which is coupled to the execution units, limits no more than one clock delay per each execution clock cycle. The control circuit further designates delay clock cycles for handling delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.