Apparatus and method with improved power-down mode
US6088806A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Oct 20, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-down circuit (72) in a lap-top computer (10) cooperates with a separate monitor circuit (80) in each of a plurality of modules (68, 74, 76) that a video-display-controller integrated circuit (36) includes. In response to various stimuli, decoding logic (78) in the power-down circuit sends respective power-down-request signals to the various monitor circuits request permission to suppress application of respective clock signals to them. If a module's operational circuitry (82) is in a state in which clock removal is safe, the monitor circuit (80) responds with an acknowledgment signal, and the power-down circuit (72) causes a clock generator to interpret application of clock signals to the respective module (68). The monitor circuit (80) may additionally detect circumstances in which removing the clock signal from the operational circuitry (82) is safe only if the clock signal can subsequently be re-applied rapidly. In those circumstances, the monitor circuit (80) generates an idle signal that causes the power-down circuit (72) to stop clocking the associated operational circuitry but continue clocking the monitor circuit. In this way, the monitor circuit can keep operating …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.