Logic circuit verification device for semiconductor integrated circuit
US6088821A · kind A · utility
20Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Mar 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic verification apparatus for a semiconductor integrated circuit classifies a program described in HDL into connection information of a synchronous circuit portion and connection information of a asynchronous circuit portion, converts a portion of the connection information of the asynchronous circuit portion into the connection information of the synchronous circuit portion and increases circuit portions the function of which can be verified by a cycle based simulation/static timing verification unit, thus making it possible to shorten the time for verification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.