Reduction of gate-induced drain leakage in semiconductor devices
US6090671A · kind A · utility
28Cited by
6References
8Claims
0Family size
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Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/91
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Reduction of gate-induced-drain-leakage in metal oxide semiconductor (MOS) devices is achieved by performing an anneal in a non-oxidizing ambient. In one embodiment, the anneal is performed in a argon and/or ammonia ambients after gate sidewall oxidation that forms the spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.