Evaluation method for wirings of semiconductor device
US6091080A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Electromigration (EM) of a multilayer wiring is evaluated accurately and efficiently. A capacitance measuring wiring is disposed through the third insulator film in parallel to the second testing wiring. A stress current is sent to the second testing wiring toward the first testing wiring for a period and subsequently the capacitance of the capacitor composed of the second testing wiring and the capacitance measuring wiring is measured. The volume of voids in the second testing wiring is obtained from the ratio of this capacitance and the capacitance before letting the stress current flow. EM is evaluated by defining the wiring life span by using this volume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.