Interleaved zero current switching in a power factor correction boost converter
US6091233A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1999 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jan 14, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for interleaving switching of multiple transistor switches in a power factor correction (PFC) boost converter and for timing the switching to occur when a current through a freewheeling diode corresponding to each switch is at a minimum level. The converter draws input current from an alternating current power supply for forming a regulated output voltage. A controller senses an input current and an output voltage across an output capacitor for controlling switching to regulate the output voltage and to ensure that the input current is substantially in phase with an input voltage. Current through a first inductor associated with a first switch is allowed to fall substantially to zero upon discharging the first inductor prior to re-charging the first inductor. Charging of a second inductor associated with a second switch, however, is initiated prior to completion of discharging the first inductor. Similarly, current through the second inductor is allowed to fall substantially to zero prior to re-charging the second inductor. An advantage is that from the perspective of the power supply, the converter operates in continuous conduction mode, while from the persp…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.