Low power clock squarer with tight duty cycle control
US6091272A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a method and apparatus for producing a square wave output signal with a clock circuit that possesses characteristics of low current consumption, relatively tight duty cycle control, and versatility over a wide range of voltages and input signal frequencies down to, and including DC. Exemplary embodiments receive an input signal, and process the input signal into an output square wave signal. A processing of the input signal is achieved using at least one current mirror for controlling a duty cycle of the output square wave signal said at least one current mirror being implemented in part with at least one pair of cascoded transistors. The processing is further achieved with an output stage having at least one inverter operatively connected with a node between the transistors of the at least one pair of cascoded transistors to control switching of the at least one pair of cascoded transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.