Integral bump technology sense resistor
US6091318A · kind A · utility
9Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 1999 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jun 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metalization layer formed as part of a bump connection/flip chip process for a semiconductor circuit is also used to form a sense resistor or other passive components. The metalization layers normal composition can also be altered so as to change or control the value of the so formed resistor or to improve the temperature stability of the resistor. Other passive components such as capacitors or inductor can also be formed in this layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.