Fast synchronous counter
US6091794A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/54
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronous counter circuit having a plurality of bit counting stages, each corresponding to a bit position for representing counts, from a least significant bit to a most significant bit. Each bit counting stage includes a flip-flip circuit and a synchronization circuit and each includes circuitry for receiving a pulse train clock signal, synchronously counting said clock signal and outputting an output bit signal corresponding to said counters' stage bit position. The bit counting stages are arranged in two groups, a reset group and a counting group, such that the output bit signal of said flip-flop circuit of the reset group synchronizes data propagation between each bit counting stage of the counting group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.