Frequency synthesis architecture in a satellite receiver
US6091931A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1997 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Jun 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip and the demodulator/decoder chip each include portions of a digital tuning frequency synthesizer. The frequency synthesizer comprises one or more digital counters which are implemented on the demodulator/decoder chip, and an oscillator which is implemented on the tuner chip. This advantageously avoids digital noise interference with the tuner chip while providing a reduced part count. Briefly, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip which cooperate to perform a frequency synthesis function. The tuner chip has a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency, and a downconverter coupled to receive a tuning frequency signal provided by the tuning oscillator. The demodulator/decoder chip has a programmable counter configured to count cycles of the tuning frequency to provide a frequency-divided signal to a phase detector. The phase detector compares the frequency-divided signal to a reference frequency, and is coupled to adjust the resonance frequency of the ta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.