Passive backplane capable of being configured to a variable data path width corresponding to a data size of the pluggable CPU board
US6092139A · kind A · utility
Inventors
Key dates
| Filing date | May 22, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | May 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a bus system having a local bus unit, a memory bus unit, an input/output bus unit, and an expansion bus unit. A pluggable central processing unit circuit board includes a microprocessor, a pluggable memory circuit board coupled to the central processing unit circuit board through the memory bus unit, and a pluggable bridge circuit board coupled to the central processing unit circuit board. A plurality of connectors includes a first connector unit for receiving the pluggable central processing unit circuit board; a second connector unit for receiving the pluggable memory circuit board; and a third connector unit for receiving the pluggable bridge circuit board. The third connector unit is coupled to the first connector unit of the central processing unit circuit board through the bus system. A plurality of peripheral devices are coupled to the bridge circuit board through the input/output bus unit. The bus system includes a variable data path width corresponding to a data size of the central processing unit circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.