Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system
US6092173A · kind A · utility
24Cited by
5References
8Claims
0Family size
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Key dates
| Filing date | Mar 26, 1997 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Mar 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.