Shared register storage mechanisms for multithreaded computer systems with out-of-order execution
US6092175A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Apr 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and organization for implementing the registers required in a computer system supporting multithreading and dynamic out-of-order execution. Multithreaded computer systems are those in which the processor supports multiple contexts (threads), and either rapid context switching from thread to thread or scheduling of instructions from different threads within a single cycle. An important component of processors for such systems is the register file; the processor needs a large register file or resource to provide the registers used for the threads. One form of the invention maintains a set of private architecturally specified registers, and a set of private renaming register for each different thread. In the other three embodiments, sharing of renaming registers between different threads is permitted, to enable a reduction in the total number of registers required. One of these three embodiments enables any of the architecturally specified registers that are private to a thread but are not in use, to be employed as renaming registers. Another of the embodiments treats all registers as sharable and enables any register from the register file or resource to be used as a renamin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.