Method for measuring latencies by randomly selected sampling of the instructions while the instruction are executed
US6092180A · kind A · utility
83Cited by
21References
18Claims
0Family size
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Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for scheduling instructions executed in a computer system including a processor and a memory subsystem, pipeline latencies and resource utilization are measured by sampling hardware while the instructions are executing. The instructions are then scheduled according to the measured latencies and resource utilizations using an instruction scheduler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.