Parallel processing of pipelined instructions having register dependencies
US6092184A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 1995 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Dec 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of processing instructions having register dependencies in a pipelined superscalar processor comprises the steps of fetching operands specified by a first instruction during a first pipestage, then computing address of a source operand for a second instruction so that the subsequent instruction can be processed without incurring data errors. A status bit of a destination register of the first instruction is checked during the decoding stages of the second instruction to determine whether the register is busy or free for use in performing the operation specified. In the case where the register is busy, processing of the subsequent instruction is temporarily frozen. In another situation, a result obtained by a first instruction is provided as a source operand for the second instruction so that the second instruction can be executed without delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.