Vertically stackable integrated circuit
US6093029A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Sep 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An arrangement for coupling a first packaged integrated circuit to a second packaged integrated circuit comprises a first packaged integrated circuit that includes a first set of electrical interconnection elements arranged on a first surface and a second set of electrical interconnection elements arranged on a second surface which is opposite to the first side. A thermally conductive material is disposed on the second surface and the second set of electrical interconnection elements are arranged around at least a portion of the periphery of the second surface. A second packaged integrated circuit includes a third set of electrical interconnection elements arranged on a first surface of the second packaged integrated circuit. The third set of electrical interconnection elements are shaped to mechanically and electrically couple and decouple to or from the second set of electrical interconnection elements non-destructively by application of manual force.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.