Method for fabricating semiconductor device with an increased process tolerance
US6093641A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 9, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Jan 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating a semiconductor device suitable for increasing process tolerance of the device are disclosed. One method includes the steps of sequentially forming an insulating layer, a planarization layer, and a nitride layer over cell transistors formed on a substrate; patterning the nitride layer to define first contact holes; forming polysilicon sidewall spacers on the sides of the patterned nitride layer; removing portions of the planarization layer and the insulating layer using the patterned nitride layer and the polysilicon sidewall spacers, so as to define second contact holes; and forming pad polysilicon layers in the second contact holes, so as to expose portions of the patterned nitride layer. Another method includes the steps of sequentially forming an insulating layer and a planarization layer over cell transistors formed on a substrate; defining pad contact holes through the insulating layer and the planarization layer; forming pad polysilicon layers in the pad contact holes; exposing portions of cap nitride layers of the cell transistors; and forming pad polysilicon sidewall spacers on the sides of the pad polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.