High speed common mode logic circuit
US6094074A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Jul 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09432
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A common mode logic (CML) circuit having an improved bias circuit and an active MOS load operating exclusively in the triode region to provide improved performance characteristics including a high speed of operation. The bias circuit of the CML circuit comprises a pair of MOS transistors, one of which has an aspect ratio (W.sub.P /L.sub.P) and the other of which has an aspect ratio (W.sub.P /L.sub.P)/n, wherein 1<n<4. This configuration causes a third MOS transistor in the bias circuit to operate exclusively in the triode region. The CML circuit also includes a logic portion, which may be a logic gate or flip-flop, having a plurality of pairs of input MOS transistors for receiving differential input signals. In accordance with the invention, the logic portion has load MOS transistors which operate exclusively in the triode region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.