Current control technique
US6094075A · kind A · utility
85Cited by
8References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Aug 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.