Current limiting receiver with impedance/load matching for a powered down receiver chip
US6094089A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 6, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Mar 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The inventive mechanism prevents current flow from the drain to the source and substrate, in a power off condition of a p-type FET. The current flow from the drain to the substrate is prevented by raising the voltage required to turn on the diodes that are formed when the power is off. This is accomplished by having the substrate gate connected to a series of diodes formed from other pFET devices. The combined threshold voltage of the series exceeds a voltage associated with the current. The current flow from the drain to the source is prevented by pinching off the channel of the pFET during a power off condition. Since a high signal is required to turn off a pFET device and the power to the pFET is off, an off chip voltage associated with the current is used to turn off the pFET. A current sink FET is used to prevent reflections by supplying the proper impedance to receive the off chip signal associated with the current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.