DRAM including an address space divided into individual blocks having memory cells activated by row address signals
US6094398A · kind A · utility
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5Claims
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Key dates
| Filing date | Mar 30, 1999 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a controller. Each individual block can then be activated by an independent activation signal derived from the row address signal. The activation signals for different blocks are supplied to the different blocks in succession with a partial time overlap, so that the obtained data rate is increased relative to activation of only one block, owing to partial time activation of at least two different blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.