Serial bus system for sending multiple frames of unique data
US6094700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Mar 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes an I/O controller and a bridge logic device which transmit status data via a serial bus. The I/O controller comprises an embedded controller, a memory device, and a serial bus interface including a transceiver, a transmit register, and a receiver register. The bridge logic also includes a serial bus interface with a transceiver, a transmit register, and a receiver register. Data is transmitted from the transmit register of one device to the receive register of the other device. Although the serial bus protocol limits data transfers to eight-bit segments, the I/O controller and bridge logic transmit up to twenty-four different variables by encoding each transmitted byte into a data frame that includes a two-bit frame identifier and a six-bit data field. Further, one of the data frames transmitted by the I/O controller includes an acknowledge bit to indicate when a previous frame has been received from the bridge logic. The bridge logic only transmits new data if the I/O controller toggles the acknowledge bit and transmits the frame containing the toggled acknowledge bit to the bridge logic. The acknowledge bit prevents the South Bridge from overwriting pre…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.