Apparatus and method for reducing data bus pin count of an interface while substantially maintaining performance
US6094711A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1997 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Jun 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The pin count of a processor is substantially reduced while effectively maintaining processor performance by using a staging register to receive and store a first data segment from a bus. A second data segment is received from the bus in a subsequent bus cycle and loaded into a cache. A steering circuit dynamically selects the transfer of the first or the second segment to a processor core, and orders positioning of the first and second data segments into the cache. In some embodiments, the cache is a first level cache and a second level cache is inserted between the bus and the processor. In these embodiments, the processor includes a bypassing circuit for designating the ordering of bus data in response to a memory access that misses the first level cache and hits the second level cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.