Digital signal processor using a reconfigurable array of macrocells
US6094726A · kind A · utility
146Cited by
14References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 5, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Feb 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A real time digital systolic processor with a core of reconfigurable interconnected macrocells which can be programmed according to function for processing high bandwidth digital data. Each macrocell contains arithmetic logic units for performing predetermined functions based on format of the input data stream from an outside source or from other macrocells. The interconnects between each macrocell are arranged so that the function of the device is predetermined according to user specific applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.