Shared memory controller having an address error detector
US6094732A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Mar 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write control unit, each time N units of data and an address indicative of a storage location next to this data is written into the shared memory, one of the written addresses is stored in a second memory provided separately from the shared memory. Each time N addresses are read from the shared memory, an address stored in the second memory is read to detect in a detector whether or not the address is erroneous. If an error is detected, the erroneous address is discarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.