Method for creating via hole in chip
US6096635A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1997 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Dec 3, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/959
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for creating via holes in a chip or a plurality of chips of a wafer is disclosed. The method is performed by using a pre-patterned transparent mask on the back of the chip or chips, and bombarding the chip(s) through the positioning holes on the transparent mask that correspond to the pre-formed pattern, with accelerated particles. According to this method, via holes can be created from the back of the chip(s) without interfering with the existing IC structure of the chip(s). The present method is highly efficient because a number of via holes can be formed simultaneously by using a large pre-pattered mask to cover the entire wafer. In addition, the present method is cost-effective because no precision apparatus is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.