Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure
US6096655A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Sep 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1026
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a dual-damascene processes for multi level interconnection a method for forming trenches and vias in the inter-insulation is accomplished without etching out the inter-insulation layer. A thick sacrificial layer is first deposited and reversed etched to form sacrificial pillars 64 forming the vias and sacrificial bridges 72 forming the trenches. The sacrificial layer can be any material (insulator, semiconductor, or metal), provided it can be easily patterned and selectively removed later over the inter insulator layer. Thereafter a low-k inter-insulation layer is deposited around the sacrificial pillars and bridges. It is these sacrificial pillars and bridges that are etched away leaving behind vias and trenches in the inter-insulation layer. An advantage of the invention is that it replaces a difficult RIE process of vias and trenches with a much easier RIE of sacrificial pillars and bridges. In the preferred embodiment, a silicon film, either amorphous or polycrystalline, is used as the sacrificial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.