ESD protection clamp for mixed voltage I/O stages using NMOS transistors

US6097071A · kind A · utility

Assignee

• Compaq Computer Corporation · US

Inventor

• David Benjamin Krakauer · Cambridge, US

Key dates

• Filing date: May 4, 1998
• Grant date: Aug 1, 2000
• Expiry date: May 4, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region. This shared diffusion region is also the common node electrically coupling the first transistor's source to the second transistor's drain region, and is a further benefit of the invention because its length controls the trigger voltage and holding voltage of the cascode transistor pair. This electrostatic discharge protection device can be used either as a self protection pull-down portion of a mixed voltag…