Electro-thermal nested die-attach design
US6097099A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1997 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49146
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A design having a semiconductor microchip bonded to a circuit board is described. This design may include: a printed circuit board (58); a semiconductor microchip (56) bonded to the circuit board (58) by means of an adhesive layer placed between the bonding surface of the microchip (56) and the desired bonding site on the circuit board (58); the adhesive layer providing for thermal relief as well as electrical contact between the microchip (56) and circuit board (58), and consisting of two or more concentric regions that adjoin but do not overlap one another; one being a center core region (50) of thermally and electrically conductive material; the other being a perimeter region (54) of thermally conductive and electrically nonconductive material surrounding the center core region (50) such that the perimeter region's (54) inner boundary completely bounds the center core region (50); and such that the perimeter region's (54) outer boundary extends to a lead on the microchip (56). Other devices, systems, and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.