System to simultaneously test trays of integrated circuit packages
US6097201A · kind A · utility
21Cited by
25References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1997 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Oct 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2887
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test system for testing numerous parts simultaneously. A stack of test boards is provided in a test chamber. Each of the test boards has a region of contactors on it. To perform a test, trays are inserted between the boards in the stack and aligned with the regions of contactors. A mechanism is then activated to press the trays towards the boards, thereby making contact between the contactors and devices on the trays. The test system is described in conjunction with a burn-in oven. Processing time is reduced because individual handling of chips is significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.