Algorithmic analog-to-digital converter with reduced differential non-linearity and method
US6097326A · kind A · utility
37Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | May 26, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | May 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/0612
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital converter section for use in an analog to digital converter which includes a converter stage which produces a digital and an residue output. The residue output is applied to an over-range stage which produces a second residue output equal to the first residue output reduced in magnitude by the magnitude of a reference voltage. The over-range stage is capable of operating with a relatively high feedback factor to increase operating speed and with commutated feedback-capacitor switching to reduce differential non-linearity errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.