Read circuit for non-volatile memories
US6097633A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Oct 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read circuit for non-volatile memories having an array section, with a corresponding bitline, and a reference section, with a corresponding reference bitline. A differential amplifier for comparing voltage signals obtained by current/voltage conversion of a current signal of an array cell and of a reference current signal is connected to the respective bit lines. A cascode transistor for each one of the array and reference sections, each driven by a NOR logic gate; a charge transistor for the bitline and a charge transistor for the reference bitline; column decoding transistors for the array section and for the reference section; the circuit further comprising an additional transistor which is connected between the NOR gate of the array side and a node for acquiring the array voltage sent to the differential amplifier, the additional transistor increasing the speed of the process for reading the bitline when the bitline is not charged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.