Nonvolatile semiconductor memory device whose addresses are selected in a multiple access
US6097666A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A block size buffer and block address pre-decoder are provided for a flash memory. At the time of data erase, the size of a block to be erased is input to the block size buffer and a set of block addresses is input to the block address pre-decoder. An output signal of the block size buffer is supplied to and decoded by the block address pre-decoder, a row decoder is controlled based on the result of pre-decoding, and a plurality of addressing including the above block address as a top address are selected in a multiple manner. Then, a plurality of successive blocks are simultaneously selected to simultaneously erase data in the memory cells in the plurality of blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.