Timing phase synchronization detecting circuit and demodulator
US6097766A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Oct 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0036
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A demodulator is made compact, and with a simple circuit arrangement, and also having a better bit error rate characteristic. A timing phase synchronization detecting circuit 219 judges any one of the following two conditions based upon baseband phase data 202, i.e., an UNLOCK (timing phase asynchronous) condition, and a LOCK (timing phase synchronous) condition. Based upon the judgement result of the timing phase synchronization detecting circuit 219, in a timing recovering means 221, a frequency range of a PLL (phase synchronization loop) is variable, whereas the number of data entered within 1 symbol time is variable in a frequency synchronizing means 222 and a carrier recovering means 223. A data demodulating means 224 outputs demodulation data 206 in response to baseband phase data 202 and a recovery carrier signal 205.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.