Low latency correlation
US6097851A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/153
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The architecture of the inventive correlator is, in a preferred embodiment, an array of correlation cells each containing a delay pipe, a math unit and an accumulator. An array of these correlation cells are tiled together to allow simultaneous processing by all cells. The array is disposed so that each cell accumulates an output value in a result surface. There is no electrical limit to the number of correlation cells that may be tiled together. A preferred embodiment uses nine cells tiled together into a 3.times.3 correlation result surface. Other embodiments have been tested in accordance with the present invention having twenty-five cells tiled together into a 5.times.5 correlation result surface. A stream of compare pixel values is presented to the array wherein each compare pixel value is presented to each cell concurrently. A reference memory supplies the appropriate reference pixel values to the cells to enable all calculations for that compare pixel value to be done concurrently. The results of those calculations are summed in each cell's accumulator. The process is repeated for each compare pixel value in the stream. When all compare pixel values in the stream have been p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.