System for reducing storage access latency with accessing main storage and data bus simultaneously
US6098115A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Apr 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method reading data from storage by speculatively accessing storage and overlapping data bus access with status determination, thereby reducing storage read access latency. Also, a system and method is provided for reducing storage read access latency by accessing a data bus substantially simultaneously with availability of data from storage. Upon receipt of a storage read request, and before status determination, the requested data is read from storage. Optionally, depending upon bus architecture or the need to minimize control circuitry, control of the data bus may speculatively be sought so that data may be loaded to the data bus upon availability from main storage, still whether or not status has been resolved. Subsequently, if status cancels the read request, further data bus loading is terminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.