Fault tolerant computer system
US6098137A · kind A · utility
34Cited by
17References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes an apparatus which enables transactions directed to a particular target device such as one situated inside a bridge to be shunted directly to the device without requiring that the transaction actually proceed to the device through a bus on which the device is located. However, the transaction may, in fact, also be run on the bus on which the device is located, the ID select for the target device may be masked. In this way, it is possible to run transactions to a particularly critical device even when the bus on which it is located is, for one reason or another, not operating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.