Thread performance analysis by monitoring processor performance event registers at thread switch
US6098169A · kind A · utility
68Cited by
5References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 23, 1997 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A thread switch handler is provided which monitors performance characteristics of a processor executing instructions from two or more threads of an application. The thread switch handler detects when the processor has switched between a first and second thread and is capable of reading the performance registers available in many commercial processors at or about that time. The data that is read from the performance registers at each thread switch represents performance characteristics of the processor on a per-thread basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.