Method and apparatus for use of a host address to validate accessed data
US6098190A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Aug 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system constructed in accordance with the invention receives data blocks and associated host LBAs from a host processor. The memory subsystem initially associates a check value with each received data block, each check value dependent upon a host LBA that is associated with the respectively received data block. The memory subsystem stores each received data block and associated check value as an "extended" data block. Thereafter, the memory subsystem, in response to a host processor request to access data corresponding to the associated host LBA, recovers the stored extended data block and determines from the check value stored therewith, if the address of the corresponding data and that provided by the host processor correspond. If the addresses correspond, the data block is transmitted to the host processor. If not, an error message is generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.