Semiconductor integrated circuit device with operation in partial depletion type mode and perfect depletion type mode
US6100565A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
MOS devices are formed on a wafer having a thick silicon layer 3a and a thin silicon layer 3b formed on a buried oxide film. The MOS device formed in the thick silicon layer 3a is activated in a partial depletion type mode. Further, the MOS device formed in the thick silicon layer 3b is activated in a perfect depletion type mode. Therefore, a low leakage current and a high-speed operation can be achieved simultaneously. It is thus possible to solve problems that an integrated circuit must be formed by either one of the partial depletion type device and the perfect depletion type device, and the low leakage current and the high-speed operation are hard to come to fruition simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.