Semiconductor chip packaging having printed circuitry or printed circuit registration feature
US6100581A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1994 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Oct 21, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit which overlies the at least one semiconductor chip in the package and extends externally of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip. The invention also relates to a method of manufacturing such a semiconductor device and to a method of assembling a semiconductor assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.