Low-voltage bus switch maintaining isolation under power-down conditions
US6100719A · kind A · utility
20Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Dec 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A control circuit for a low-voltage bus switch where the control circuit keeps the bus switch open by stealing power from switch I/O terminals during the loss of supply voltage and thereby maintaining bus isolation. The control circuit also provides a good high level and presents a low switch impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.