Frequency doubler using digital delay lock loop
US6100736A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1997 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Jun 5, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase comparator compares phase of a clock signal and a generated comparison clock signal based upon rising edges. The output of the phase comparator may include a series of short up (U) pulses or down (D) pulses, depending whether the phase of the comparison clock is leading or lagging the clock. Up and down pulses U and D control an up/down shift register which in turn compensates phase difference by inserting or removing additional discrete delay elements in a variable delay line. Based upon delay signals generated by the variable delay line, a double frequency clock generator generates a 2.times. clock signal. The 2.times. clock signal is divided by 2 in a divider to supply the phase comparator with the generated comparison clock signal. The feedback scheme helps the digital delay lock loop of stabilize after a few clock cycles without additional external control. The use of digital delay elements in the delay lock loop eliminates the need for large analog circuits used in PLLs, and thus saves silicon (wafer) space. In addition, the digital circuitry of the present invention consumes less power than a comparable analog PLL. Moreover, the circuit of the present invention will …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.