Method and apparatus for reducing power supply current surges in a charge pump using a delayed clock line
US6100752A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1997 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Sep 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/07
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention is a charge pump circuit to reduce and distribute power supply current surges. The charge pump circuit includes a first clock line to provide a first clock thereon, a plurality of delay circuits connected in series, each delay circuit generating a delayed and inverted clock from its input clock on a respective output clock line, and a plurality of charge pump stages connected in series each to store charge thereon. The first clock line is coupled to the first charge pump stage and the plurality of output clock lines are coupled to a respective plurality of remaining charge pump stages. The operation of each charge pump stage is staggered to reduce and distribute the power supply current surges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.