Recursive multi-bit ADC with predictor
US6100834A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | May 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flash converter is preceded by an accurate continuous-time error amplifier operating on the difference between the input signal and a feedback DAC. The DAC output is operatively coupled to the amplifier input virtual ground or summing node through, for example, a set of precision capacitors. The input circuit is also coupled to the amplifier input through a continuous-time element such as a set of precision capacitors, approximately equal in capacitance to those coupled to the DAC. The amplifier may have a moderate closed-loop forward gain such as 16 with a high-pass characteristic beyond, for example, 10 Hz. The DAC is controlled by the latched output of a digital signal processing block, which uses digital outputs from the flash converter and the last latched output to predict the next value of the input signal. Converter control loop stability is afforded by providing a lowpass character to the prediction circuit. The converter produces a digital result by adding the digital value produced by the flash, properly scaled, to the current digital output value of the digital latch driving the DAC. The digital result may be sub-sampled at any arbitrary phase of the input sampling cl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.