Semiconductor memory device
US6101120A · kind A · utility
6Cited by
5References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1999 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Jul 19, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device which can reduce the size of a memory cell and increase the packing density is disclosed. Each memory cell comprises a p-type active region, an n-type active region, two word lines, a common gate line and a common gate line. Two memory cells are deviated by, for example, an amount of a half bit in the direction which perpendicularly crosses the word line direction. The memory cells are arranged with one of their parts overlapped with one another in the word line direction. Thus, the size of the memory cell can be reduced in the word line direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.