Data latch circuit
US6101122A · kind A · utility
2Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 22, 1999 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Mar 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data latch circuit includes a differential amplifier for detecting a potential difference between a pair of signal transmission lines for transmitting a pair of complementary signals, a latch timing signal generator for generating a latch timing signal based on the detection by the differential amplifier, and a latch section for responding to the latch timing signal to latch the complementary signals transferred thereto. A reliable and high-speed signal transmission can be achieved even in a semiconductor device having a large chip size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.