Semiconductor device memory cell and method for selectively erasing the same
US6101130A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1999 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Jun 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.